1. Field of the Invention
The present invention relates to a design of a semiconductor device. In particular, the present invention relates to a design of a semiconductor device having a common semiconductor active region provided between two gate electrodes.
2. Discussion of the Related Art
Dual-gate semiconductor devices have been proposed for non-volatile semiconductor memories such as NAND-type or NOR-type electrically erasable and programmable non-volatile memory (“flash memory”) cells. One example of such a dual-gate flash memory cell is disclosed in U.S. Pat. No. 6,054,734 to Aozasa et al., entitled “Non-volatile Memory Cell Having Dual-gate Electrodes,” filed on Nov. 5, 1997 and issued on Apr. 25, 2000. The '734 patent discloses that a dual-gate semiconductor device allows better control over its threshold voltage, particularly when the feature size is less than 0.1 μm.
A dual-gate memory cell disclosed in FIG. 4 of the '734 patent is reproduced herein as FIG. 1 to illustrate such a memory cell of the prior art. As shown in FIG. 1, dual-gate memory cell 22 includes first gate electrode 36 formed in insulating layer 26, which is supported by supporting substrate 24 (e.g., a semiconductor wafer). Insulating layer 32—which includes a silicon nitride charge storage layer formed as a part of an oxide-nitride-oxide (ONO) multilayer structure—forms an insulating layer between first gate 36 and active semiconductor region 30. Active region 30 may be formed using mono-crystalline silicon. Second gate electrode 38 is formed on the other side of active region 30 and is insulated from active region 30 by gate insulating layer 34. Source-drain regions 40 and 42 are provided at the periphery of active region 30, which may be interconnected with other circuitry on the same substrate through interconnection layers 44 and 46.
Dual-gate memory cell 22 thus constitutes a combination of a memory device, controlled by first gate electrode 36, and a non-memory device, controlled by second gate electrode 38. Typically, gate electrode 36 is coupled to a word line, and source-drain regions 40 and 42 are coupled by interconnection material 44 and 46 to the bit line and a source reference voltage. Programming and erasing of dual-gate memory cell is achieved by applying predetermined voltage levels across the word line coupled to first gate electrode 36 and the bit line and the reference voltage coupled to source-drain regions 40 and 42. In dual-gate memory cell 22, the programmed state of the memory device affects the threshold voltage of the non-memory device. The '734 patent teaches using this electrostatic interaction to “read” or detect the programmed state of the memory cell. Specifically, the '734 patent teaches providing active region 30 to be on the order of the depletion layer thickness of the memory device, such that the threshold voltage of the non-memory device depends on whether or not the memory device is in an erased state or a programmed state.
A NAND-type memory circuit is typically organized using strings of memory cells (“NAND strings”), with each NAND string being formed by serially connecting the source-drain regions of a number of the memory cells between a bit line and a source line. Dual-gate memory cell 22 is not entirely satisfactory as a building block for forming such NAND strings in a memory circuit. This is because, to program such a string, in addition to applying the programming voltage to the memory cell to be programmed, the word line of each non-selected memory cell is required to be biased to an intermediate voltage (“program pass voltage”) so that active region 30 in each of the non-selected memory cells is conducting. The conducting non-selected memory cells allow source-drain regions 40 and 42 of the selected memory cell to be properly biased. This program pass voltage is carefully chosen in the window between the programming voltage and zero volts to avoid modifying the programmed state of the non-selected memory cells to any extent. The non-selected dual-gate memory cells in the NAND strings are thus susceptible to “program disturb”, as a result of the program pass voltage imposed at their gate electrodes.
The non-memory device (i.e., the device controlled by gate electrode 38) may be used either alone or in conjunction with the memory device (i.e., the device controlled by gate electrode 36) to ensure that active region 30 is conducting in each of the non-selected memory cells. The electrical interaction between the devices on opposite surfaces of active region 30, however, causes “program disturb” in the non-selected dual-gate memory cells of the NAND string.
Similarly, during a read operation, active region 30 of each non-selected dual-gate memory cell in such a NAND string is also rendered conducting by applying a “read pass voltage” to the gate electrodes of the non-memory devices. The resulting electrostatic interaction between the two devices on opposite faces of active region 30 disturbs the stored charge in the non-selected memory devices (“read disturb”).
In the prior art, program/read verify schemes, such as those taught in the '734 patent for the dual-gate NAND string (and also for standard single-gate NAND strings) are devised to ensure that the programmed memory cell is charged to reach a well-defined minimum threshold voltage above the distribution of erased threshold voltages and to ensure that no memory cell in the NAND string is programmed beyond a well-defined maximum threshold voltage. In this manner, during subsequent read operations, a relatively low “read pass voltage” may be used to allow the non-selected devices to conduct. Program/read verify schemes often utilize a combination of time-consuming read operations and applications of multiple programming pulses. These activities limit the “program bandwidth” (i.e., the rate at which a memory chip can be programmed).
The '734 patent requires the effect of stored charge in the memory device to be read out as a change in the threshold voltage of the opposite non-memory device. While this method certainly reduces one component of read disturb, it also reduces the effective threshold voltage window between programmed and erased states to less than half of what it would have been if the threshold voltage of the memory device itself is measured in the read operation.
The three methods outlined in the '734 patent to form the dual-gate device and, in particular, the thin active region 30 with source and drain regions 40 and 42, include (1) “bonding SOI”, (2) a technique based on lateral epitaxial growth from the substrate as seed, and (3) a technique based on implantation. Such techniques are relatively expensive and do not allow stacking additional memory cell layers in three dimensions. Thus, a memory circuit based on dual-gate memory cell 22 of the '734 patent is limited in the circuit density it can achieve.
Furthermore, the above methods constrain peripheral circuitry to the same layer as the memory cells and result in the substrate acting purely as a mechanical support, thus further limiting the circuit density that can be achieved.
Thus, it is desired to have a high density memory device using a dual-gate structure which can achieve a high circuit density, and which, when used in the context of a non-volatile memory cell, is less susceptible to the disadvantages of program and read disturbs and reduces the need for time-consuming program/read verify schemes.